Challenges In Scaling Chips To 2nm And Below

Key Takeaways

  • Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly.
  • Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages.
  • New levels of precision are required throughout the design-through-manufacturing flow, resulting in shifts to some technologies that have been sitting on the sidelines for years.

Designing, developing, and manufacturing chips at 2nm and below requires a whole new set of business and technology tradeoffs that are dramatically more impactful at every turn, from architectural inception to manufacturing yield.

The primary goal of shrinking features at these dimensions is…

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